Synthesis of Asynchronous Circuits with Predictable Latency. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Alexandre_V._Bystrov>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Alexandre_Yakovlev>
dc:identifier	DBLP conf/iwls/BystrovY02 (xsd:string)
dcterms:issued	2002 (xsd:gYear)
rdfs:label	Synthesis of Asynchronous Circuits with Predictable Latency. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Alexandre_V._Bystrov>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Alexandre_Yakovlev>
swrc:pages	239-243 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/iwls/2002>
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dc:title	Synthesis of Asynchronous Circuits with Predictable Latency. (xsd:string)
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rdf:type	swrc:InProceedings
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