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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iwls/ShelarS02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rupesh_S._Shelar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
dc:identifier DBLP conf/iwls/ShelarS02 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rupesh_S._Shelar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
swrc:pages 209-214 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iwls/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iwls/ShelarS02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iwls/ShelarS02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iwls/iwls2002.html#ShelarS02>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iwls>
dc:title Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document