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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iwsoc/Khadanga03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Suchitav_Khadanga>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIWSOC.2003.1213049>
foaf:homepage <https://doi.org/10.1109/IWSOC.2003.1213049>
dc:identifier DBLP conf/iwsoc/Khadanga03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIWSOC.2003.1213049 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Synchronous programmable divider design for PLL Using 0.18 um cmos technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Suchitav_Khadanga>
swrc:pages 281-286 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iwsoc/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iwsoc/Khadanga03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iwsoc/Khadanga03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iwsoc/iwsoc2003.html#Khadanga03>
rdfs:seeAlso <https://doi.org/10.1109/IWSOC.2003.1213049>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iwsoc>
dc:subject CMOS integrated circuits, frequency synthesizers, phase locked loop, programmable divider, Prescaler, PLL. (xsd:string)
dc:title Synchronous programmable divider design for PLL Using 0.18 um cmos technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document