Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iwsoc/TakoudaAV05
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Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization.
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Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization.
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