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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/lascas/KesslerBRPC22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Henrique_Kessler>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leomar_S._da_Rosa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcelo_Schiavon_Porto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Murilo_Bohlke>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinicius_V._Camargo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FLASCAS53948.2022.9789079>
foaf:homepage <https://doi.org/10.1109/LASCAS53948.2022.9789079>
dc:identifier DBLP conf/lascas/KesslerBRPC22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FLASCAS53948.2022.9789079 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Henrique_Kessler>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leomar_S._da_Rosa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcelo_Schiavon_Porto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Murilo_Bohlke>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinicius_V._Camargo>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/lascas/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/lascas/KesslerBRPC22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/lascas/KesslerBRPC22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/lascas/lascas2022.html#KesslerBRPC22>
rdfs:seeAlso <https://doi.org/10.1109/LASCAS53948.2022.9789079>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/lascas>
dc:title Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document