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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/latw/GaillardonGM13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Giovanni_De_Micheli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hassan_Ghasemzadeh_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pierre-Emmanuel_Gaillardon>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FLATW.2013.6562673>
foaf:homepage <https://doi.org/10.1109/LATW.2013.6562673>
dc:identifier DBLP conf/latw/GaillardonGM13 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FLATW.2013.6562673 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
rdfs:label Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giovanni_De_Micheli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hassan_Ghasemzadeh_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pierre-Emmanuel_Gaillardon>
swrc:pages 1-6 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/latw/latw2013.html#GaillardonGM13>
rdfs:seeAlso <https://doi.org/10.1109/LATW.2013.6562673>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/latw>
dc:title Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document