Integrated CPU and l2 cache voltage scaling using machine learning.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/lctrts/AbouGhazalehFRXLCMM07
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/lctrts/AbouGhazalehFRXLCMM07
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Alexandre_Peixoto_Ferreira
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Bruce_R._Childers
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Cosmin_Rusu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Moss%E2%88%9A%C2%A9
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Frank_Liberato
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Nevine_AbouGhazaleh
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Rami_G._Melhem
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ruibin_Xu
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1254766.1254773
>
foaf:
homepage
<
https://doi.org/10.1145/1254766.1254773
>
dc:
identifier
DBLP conf/lctrts/AbouGhazalehFRXLCMM07
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1254766.1254773
(xsd:string)
dcterms:
issued
2007
(xsd:gYear)
rdfs:
label
Integrated CPU and l2 cache voltage scaling using machine learning.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Alexandre_Peixoto_Ferreira
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Bruce_R._Childers
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Cosmin_Rusu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Moss%E2%88%9A%C2%A9
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Frank_Liberato
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Nevine_AbouGhazaleh
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Rami_G._Melhem
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ruibin_Xu
>
swrc:
pages
41-50
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/lctrts/2007
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/lctrts/AbouGhazalehFRXLCMM07/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/lctrts/AbouGhazalehFRXLCMM07
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/lctrts/lctes2007.html#AbouGhazalehFRXLCMM07
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1254766.1254773
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/lctrts
>
dc:
subject
integrated DVS policy, machine learning, multiple clock domains, power management
(xsd:string)
dc:
title
Integrated CPU and l2 cache voltage scaling using machine learning.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document