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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/lctrts/KimVKI03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyun_Suk_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mahmut_T._Kandemir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mary_Jane_Irwin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Narayanan_Vijaykrishnan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F780732.780770>
foaf:homepage <https://doi.org/10.1145/780732.780770>
dc:identifier DBLP conf/lctrts/KimVKI03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F780732.780770 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Adapting instruction level parallelism for optimizing leakage in VLIW architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyun_Suk_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mahmut_T._Kandemir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mary_Jane_Irwin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Narayanan_Vijaykrishnan>
swrc:pages 275-283 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/lctrts/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/lctrts/KimVKI03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/lctrts/KimVKI03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/lctrts/lctes2003.html#KimVKI03>
rdfs:seeAlso <https://doi.org/10.1145/780732.780770>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/lctrts>
dc:subject VLIW architecture, functional units, instruction level parallelism, instruction scheduling, leakage energy, power supply gating (xsd:string)
dc:title Adapting instruction level parallelism for optimizing leakage in VLIW architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document