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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/lctrts/Krishnaswamy03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arvind_Krishnaswamy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajiv_Gupta_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F780732.780767>
foaf:homepage <https://doi.org/10.1145/780732.780767>
dc:identifier DBLP conf/lctrts/Krishnaswamy03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F780732.780767 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Enhancing the performance of 16-bit code using augmenting instructions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arvind_Krishnaswamy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajiv_Gupta_0001>
swrc:pages 254-264 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/lctrts/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/lctrts/Krishnaswamy03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/lctrts/Krishnaswamy03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/lctrts/lctes2003.html#Krishnaswamy03>
rdfs:seeAlso <https://doi.org/10.1145/780732.780767>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/lctrts>
dc:subject 16-bit thumb ISA, 32-bit ARM ISA, AX instructions, code size, embedded processor, instruction coalescing, performance (xsd:string)
dc:title Enhancing the performance of 16-bit code using augmenting instructions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document