Bypass aware instruction scheduling for register file power reduction.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/lctrts/ParkSDNPE06
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Bypass aware instruction scheduling for register file power reduction.
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architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, power consumption, processor bypasses, register file, reservation table
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Bypass aware instruction scheduling for register file power reduction.
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