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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/mdis/FloreaV20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Adrian_Florea>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teodora_Vasilas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-030-68527-0%5F3>
foaf:homepage <https://doi.org/10.1007/978-3-030-68527-0_3>
dc:identifier DBLP conf/mdis/FloreaV20 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-030-68527-0%5F3 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Optimizing the Integration Area and Performance of VLIW Architectures by Hardware/Software Co-design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Adrian_Florea>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Teodora_Vasilas>
swrc:pages 35-51 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/mdis/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/mdis/FloreaV20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/mdis/FloreaV20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/mdis/mdis2020.html#FloreaV20>
rdfs:seeAlso <https://doi.org/10.1007/978-3-030-68527-0_3>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/mdis>
dc:title Optimizing the Integration Area and Performance of VLIW Architectures by Hardware/Software Co-design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document