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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/memsys/CilasunMPSG22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhik_Sarkar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_Macaraeg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/H%E2%88%9A%C4%BEsrev_Cilasun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ivy_Bo_Peng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maya_B._Gokhale>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3565053.3565061>
foaf:homepage <https://doi.org/10.1145/3565053.3565061>
dc:identifier DBLP conf/memsys/CilasunMPSG22 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3565053.3565061 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label FPGA-accelerated simulation of variable latency memory systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhik_Sarkar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_Macaraeg>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/H%E2%88%9A%C4%BEsrev_Cilasun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ivy_Bo_Peng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maya_B._Gokhale>
swrc:pages 8:1-8:11 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/memsys/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/memsys/CilasunMPSG22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/memsys/CilasunMPSG22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/memsys/memsys2022.html#CilasunMPSG22>
rdfs:seeAlso <https://doi.org/10.1145/3565053.3565061>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/memsys>
dc:title FPGA-accelerated simulation of variable latency memory systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document