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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/memsys/KerseyYK15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chad_D._Kersey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyesoon_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_Yalamanchili>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F2818950.2818954>
foaf:homepage <https://doi.org/10.1145/2818950.2818954>
dc:identifier DBLP conf/memsys/KerseyYK15 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F2818950.2818954 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chad_D._Kersey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyesoon_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_Yalamanchili>
swrc:pages 29-30 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/memsys/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/memsys/KerseyYK15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/memsys/KerseyYK15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/memsys/memsys2015.html#KerseyYK15>
rdfs:seeAlso <https://doi.org/10.1145/2818950.2818954>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/memsys>
dc:title SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document