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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/memsys/ShangLSSY19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Yang_0006>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming_Ling>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shan_Shen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianxiang_Shao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaojing_Shang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3357526.3357535>
foaf:homepage <https://doi.org/10.1145/3357526.3357535>
dc:identifier DBLP conf/memsys/ShangLSSY19 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3357526.3357535 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Yang_0006>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming_Ling>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shan_Shen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianxiang_Shao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaojing_Shang>
swrc:pages 451-458 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/memsys/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/memsys/ShangLSSY19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/memsys/ShangLSSY19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/memsys/memsys2019.html#ShangLSSY19>
rdfs:seeAlso <https://doi.org/10.1145/3357526.3357535>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/memsys>
dc:title RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document