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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/micro/BondiND96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_O._Bondi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Simonjit_Dutta>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FMICRO.1996.566446>
foaf:homepage <https://doi.org/10.1109/MICRO.1996.566446>
dc:identifier DBLP conf/micro/BondiND96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FMICRO.1996.566446 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_O._Bondi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Simonjit_Dutta>
swrc:pages 14-23 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/micro/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/micro/BondiND96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/micro/BondiND96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/micro/micro96.html#BondiND96>
rdfs:seeAlso <https://doi.org/10.1109/MICRO.1996.566446>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/micro>
dc:subject branch target buffer technology, deep pipelines, microprocessor chips, microprocessor designs, misprediction recovery cache integration, multiple instructions, performance loss, residual misprediction penalty, superscalar pipeline (xsd:string)
dc:title Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document