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SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, compiler, computer architecture, copies, gcc-generated optimized SPARC code, high-performance VLIW code, loop unrolling, memory disambiguation, nongreedy enhanced pipeline scheduling, nonspeculative operations, parallel machines, performance, profile-based all-path speculation, renaming, restricted speculative loads, scheduling compiler, scheduling techniques, software pipelining, speculative operations, trace-based speculation
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