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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/micro/ValeroSPLCLD09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alejandro_Valero>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Duato>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Julio_Sahuquillo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pedro_L%E2%88%9A%E2%89%A5pez_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ramon_Canal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Salvador_Petit>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vicente_Lorente>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1669112.1669140>
foaf:homepage <https://doi.org/10.1145/1669112.1669140>
dc:identifier DBLP conf/micro/ValeroSPLCLD09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1669112.1669140 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label An hybrid eDRAM/SRAM macrocell to implement first-level data caches. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alejandro_Valero>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Duato>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Julio_Sahuquillo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pedro_L%E2%88%9A%E2%89%A5pez_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ramon_Canal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Salvador_Petit>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vicente_Lorente>
swrc:pages 213-221 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/micro/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/micro/ValeroSPLCLD09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/micro/ValeroSPLCLD09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/micro/micro2009.html#ValeroSPLCLD09>
rdfs:seeAlso <https://doi.org/10.1145/1669112.1669140>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/micro>
dc:subject leakage current, retention time, static and dynamic memory cells (xsd:string)
dc:title An hybrid eDRAM/SRAM macrocell to implement first-level data caches. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document