Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/micro/ZhaoDZY09
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2009
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Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.
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3D die stacking, DRAM, NUCA, process variation
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Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.
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