Xar-trek: run-time execution migration among FPGAs and heterogeneous-ISA CPUs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/middleware/HortaCVPBOR21
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/middleware/HortaCVPBOR21
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Antonio_Barbalace
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Binoy_Ravindran
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Cesar_Philippidis
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Edson_Horta
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ho-Ren_Chuang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Naarayanan_Rao_VSathish
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Pierre_Olivier
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F3464298.3493388
>
foaf:
homepage
<
https://doi.org/10.1145/3464298.3493388
>
dc:
identifier
DBLP conf/middleware/HortaCVPBOR21
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F3464298.3493388
(xsd:string)
dcterms:
issued
2021
(xsd:gYear)
rdfs:
label
Xar-trek: run-time execution migration among FPGAs and heterogeneous-ISA CPUs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Antonio_Barbalace
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Binoy_Ravindran
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Cesar_Philippidis
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Edson_Horta
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ho-Ren_Chuang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Naarayanan_Rao_VSathish
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Pierre_Olivier
>
swrc:
pages
104-118
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/middleware/2021
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/middleware/HortaCVPBOR21/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/middleware/HortaCVPBOR21
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/middleware/middleware2021.html#HortaCVPBOR21
>
rdfs:
seeAlso
<
https://doi.org/10.1145/3464298.3493388
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/middleware
>
dc:
title
Xar-trek: run-time execution migration among FPGAs and heterogeneous-ISA CPUs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document