Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m).
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/mobility/ChenLL08
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2008
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Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m).
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bit-parallel systolic multiplier, hankel matrix-vector, montgomery, normal bases
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Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m).
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