Design of a Digital PLL Real Number Model Using SystemVerilog. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Alkiviadis_A._Hatzopoulos>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Nikolaos_Georgoulopoulos>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FMOCAST.2019.8741595>
foaf:homepage	<https://doi.org/10.1109/MOCAST.2019.8741595>
dc:identifier	DBLP conf/mocast/Georgoulopoulos19 (xsd:string)
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dcterms:issued	2019 (xsd:gYear)
rdfs:label	Design of a Digital PLL Real Number Model Using SystemVerilog. (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/mocast/mocast2019.html#Georgoulopoulos19>
rdfs:seeAlso	<https://doi.org/10.1109/MOCAST.2019.8741595>
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dc:title	Design of a Digital PLL Real Number Model Using SystemVerilog. (xsd:string)
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