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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/msr/SudakrishnanMWR08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/E._James_Whitehead_Jr.>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Janaki_T._Madhavan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jose_Renau>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sangeetha_Sudhakrishnan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1370750.1370761>
foaf:homepage <https://doi.org/10.1145/1370750.1370761>
dc:identifier DBLP conf/msr/SudakrishnanMWR08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1370750.1370761 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Understanding bug fix patterns in verilog. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/E._James_Whitehead_Jr.>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Janaki_T._Madhavan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jose_Renau>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sangeetha_Sudhakrishnan>
swrc:pages 39-42 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/msr/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/msr/SudakrishnanMWR08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/msr/SudakrishnanMWR08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/msr/msr2008.html#SudakrishnanMWR08>
rdfs:seeAlso <https://doi.org/10.1145/1370750.1370761>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/msr>
dc:subject VHDL, error classification, verilog (xsd:string)
dc:title Understanding bug fix patterns in verilog. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document