Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/mwscas/SuzukiNH12
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/mwscas/SuzukiNH12
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Daisuke_Suzuki
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Masanori_Natsui
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Takahiro_Hanyu
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FMWSCAS.2012.6292025
>
foaf:
homepage
<
https://doi.org/10.1109/MWSCAS.2012.6292025
>
dc:
identifier
DBLP conf/mwscas/SuzukiNH12
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FMWSCAS.2012.6292025
(xsd:string)
dcterms:
issued
2012
(xsd:gYear)
rdfs:
label
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Daisuke_Suzuki
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Masanori_Natsui
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Takahiro_Hanyu
>
swrc:
pages
334-337
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/mwscas/2012
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/mwscas/SuzukiNH12/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/mwscas/SuzukiNH12
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/mwscas/mwscas2012.html#SuzukiNH12
>
rdfs:
seeAlso
<
https://doi.org/10.1109/MWSCAS.2012.6292025
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/mwscas
>
dc:
title
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document