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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/mwscas/VemulaHC17a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lohith_Kumar_Vemula>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masud_H._Chowdhury>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nahid_M._Hossain>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FMWSCAS.2017.8053024>
foaf:homepage <https://doi.org/10.1109/MWSCAS.2017.8053024>
dc:identifier DBLP conf/mwscas/VemulaHC17a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FMWSCAS.2017.8053024 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Emerging STT-MRAM circuit and architecture co-design in 45nm technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lohith_Kumar_Vemula>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masud_H._Chowdhury>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nahid_M._Hossain>
swrc:pages 719-722 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/mwscas/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/mwscas/VemulaHC17a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/mwscas/VemulaHC17a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/mwscas/mwscas2017.html#VemulaHC17a>
rdfs:seeAlso <https://doi.org/10.1109/MWSCAS.2017.8053024>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/mwscas>
dc:title Emerging STT-MRAM circuit and architecture co-design in 45nm technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document