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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/mwscas/YangO18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Erdal_Oruklu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muyu_Yang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FMWSCAS.2018.8623926>
foaf:homepage <https://doi.org/10.1109/MWSCAS.2018.8623926>
dc:identifier DBLP conf/mwscas/YangO18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FMWSCAS.2018.8623926 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Erdal_Oruklu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muyu_Yang>
swrc:pages 420-423 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/mwscas/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/mwscas/YangO18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/mwscas/YangO18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/mwscas/mwscas2018.html#YangO18>
rdfs:seeAlso <https://doi.org/10.1109/MWSCAS.2018.8623926>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/mwscas>
dc:title Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document