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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/nanonet/VenkataratnamG06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aranggan_Venkataratnam>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashok_K._Goel_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FNANONET.2006.346218>
foaf:homepage <https://doi.org/10.1109/NANONET.2006.346218>
dc:identifier DBLP conf/nanonet/VenkataratnamG06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FNANONET.2006.346218 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aranggan_Venkataratnam>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashok_K._Goel_0001>
swrc:pages 1-5 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/nanonet/nanonet2006.html#VenkataratnamG06>
rdfs:seeAlso <https://doi.org/10.1109/NANONET.2006.346218>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/nanonet>
dc:title Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document