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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/natw/PlattL18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chen_Liu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Timothy_M._Platt>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FNATW.2018.8388864>
foaf:homepage <https://doi.org/10.1109/NATW.2018.8388864>
dc:identifier DBLP conf/natw/PlattL18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FNATW.2018.8388864 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Reducing test time with FPGA accelerators using OpenCL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chen_Liu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Timothy_M._Platt>
swrc:pages 1-9 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/natw/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/natw/PlattL18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/natw/PlattL18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/natw/natw2018.html#PlattL18>
rdfs:seeAlso <https://doi.org/10.1109/NATW.2018.8388864>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/natw>
dc:title Reducing test time with FPGA accelerators using OpenCL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document