Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
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2003
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Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
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High performance computing, Massively parallel computing, Fault-tolerant memory, Built-in-self-repair (BISR), Yield, Reliability, Field Reconfiguration, Modular Redundancy, HW/SW Co-reliability, Reliability Assurance
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Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
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