Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Anastacia_B._Alvarez>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Arcel_G._Leynes>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Chris_Vincent_J._Densing>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Fredrick_Angelo_R._Galapon>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/John_Richard_E._Hizon>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Lemuel_Neil_M._Noveno>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Marc_D._Rosales>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Maria_Theresa_G._de_Leon>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Mark_Allen_D._C._Agaton>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Rico_Jossel_M._Maestro>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FNGCAS.2018.8572265>
foaf:homepage	<https://doi.org/10.1109/NGCAS.2018.8572265>
dc:identifier	DBLP conf/ngcas/GalaponALNADHRL18 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FNGCAS.2018.8572265 (xsd:string)
dcterms:issued	2018 (xsd:gYear)
rdfs:label	Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Chris_Vincent_J._Densing>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Fredrick_Angelo_R._Galapon>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/John_Richard_E._Hizon>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Lemuel_Neil_M._Noveno>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Marc_D._Rosales>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Maria_Theresa_G._de_Leon>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Mark_Allen_D._C._Agaton>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Rico_Jossel_M._Maestro>
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rdfs:seeAlso	<https://doi.org/10.1109/NGCAS.2018.8572265>
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dc:title	Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. (xsd:string)
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