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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/niles/El-MaksoudMTAEK21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abdallah_Mohamed>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ahmed_J._Abd_El-Maksoud>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ahmed_Tarek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Amr_Adel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Amr_Eid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eman_El_Mandouh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Farida_Khaled>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fatma_Khaled>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hassan_Mostafa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ziad_Ibrahim>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FNILES53778.2021.9600555>
foaf:homepage <https://doi.org/10.1109/NILES53778.2021.9600555>
dc:identifier DBLP conf/niles/El-MaksoudMTAEK21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FNILES53778.2021.9600555 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abdallah_Mohamed>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ahmed_J._Abd_El-Maksoud>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ahmed_Tarek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amr_Adel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amr_Eid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eman_El_Mandouh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Farida_Khaled>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fatma_Khaled>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hassan_Mostafa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ziad_Ibrahim>
swrc:pages 376-379 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/niles/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/niles/El-MaksoudMTAEK21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/niles/El-MaksoudMTAEK21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/niles/niles2021.html#El-MaksoudMTAEK21>
rdfs:seeAlso <https://doi.org/10.1109/NILES53778.2021.9600555>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/niles>
dc:title FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document