Reducing the Interconnection Network Cost of Chip Multiprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/nocs/AbadPG08
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/nocs/AbadPG08
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9-%E2%88%9A%C4%80ngel_Gregorio
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Pablo_Abad_Fidalgo
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Valentin_Puente
>
foaf:
homepage
<
http://dx.doi.org/doi.ieeecomputersociety.org%2F10.1109%2FNOCS.2008.10
>
foaf:
homepage
<
https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.10
>
dc:
identifier
DBLP conf/nocs/AbadPG08
(xsd:string)
dc:
identifier
DOI doi.ieeecomputersociety.org%2F10.1109%2FNOCS.2008.10
(xsd:string)
dcterms:
issued
2008
(xsd:gYear)
rdfs:
label
Reducing the Interconnection Network Cost of Chip Multiprocessors.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9-%E2%88%9A%C4%80ngel_Gregorio
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Pablo_Abad_Fidalgo
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Valentin_Puente
>
swrc:
pages
183-192
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/nocs/2008
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/nocs/AbadPG08/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/nocs/AbadPG08
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/nocs/nocs2008.html#AbadPG08
>
rdfs:
seeAlso
<
https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.10
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/nocs
>
dc:
subject
Router Design, Chip Multiprocessors, Deadlock
(xsd:string)
dc:
title
Reducing the Interconnection Network Cost of Chip Multiprocessors.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document