An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/nocs/PlanaBFSSW08
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An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
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GALS, Synchonizer, Bandwidth aggregation, source-address routing
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An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
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