FPGA-based real-time receiver for Nyquist-FDM at 112 Gbit/s sampled with 32 GSa/s.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ofc/BaeuerleJEDHL17
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FPGA-based real-time receiver for Nyquist-FDM at 112 Gbit/s sampled with 32 GSa/s.
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FPGA-based real-time receiver for Nyquist-FDM at 112 Gbit/s sampled with 32 GSa/s.
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