A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ofc/HuYYSZWWBWXPYLC19
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A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die.
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