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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ofc/ManiotisFKP14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Fitsios>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/George_T._Kanellos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikos_Pleros>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pavlos_Maniotis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1364%2FOFC.2014.Th2A.6>
foaf:homepage <https://doi.org/10.1364/OFC.2014.Th2A.6>
dc:identifier DBLP conf/ofc/ManiotisFKP14 (xsd:string)
dc:identifier DOI doi.org%2F10.1364%2FOFC.2014.Th2A.6 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._Fitsios>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/George_T._Kanellos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikos_Pleros>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pavlos_Maniotis>
swrc:pages 1-3 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ofc/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ofc/ManiotisFKP14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ofc/ManiotisFKP14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ofc/ofc2014.html#ManiotisFKP14>
rdfs:seeAlso <https://doi.org/10.1364/OFC.2014.Th2A.6>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ofc>
dc:title A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document