A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory.
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/paap/0005SZ19
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Feng_Shi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hong_Zhang_0036
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Xiaojun_Wang_0005
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2F978-981-15-2767-8%5F4
>
foaf:
homepage
<
https://doi.org/10.1007/978-981-15-2767-8_4
>
dc:
identifier
DBLP conf/paap/0005SZ19
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2F978-981-15-2767-8%5F4
(xsd:string)
dcterms:
issued
2019
(xsd:gYear)
rdfs:
label
A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Feng_Shi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hong_Zhang_0036
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Xiaojun_Wang_0005
>
swrc:
pages
35-47
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/paap/2019
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/paap/0005SZ19/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/paap/0005SZ19
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/paap/paap2019.html#0005SZ19
>
rdfs:
seeAlso
<
https://doi.org/10.1007/978-981-15-2767-8_4
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/paap
>
dc:
title
A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document