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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/pact/TrinitisKWS09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Carsten_Trinitis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jasmin_Smajic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Josef_Weidendorfer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tilman_K%E2%88%9A%C4%BEstner>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-03275-2%5F5>
foaf:homepage <https://doi.org/10.1007/978-3-642-03275-2_5>
dc:identifier DBLP conf/pact/TrinitisKWS09 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-03275-2%5F5 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Sparse Matrix Operations on Multi-core Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Carsten_Trinitis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jasmin_Smajic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Josef_Weidendorfer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tilman_K%E2%88%9A%C4%BEstner>
swrc:pages 41-48 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/pact/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/pact/TrinitisKWS09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/pact/TrinitisKWS09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/pact/pact2009.html#TrinitisKWS09>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-03275-2_5>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/pact>
dc:subject Multi-core; pinning; cache optimization; performance optimization; sparse matrices (xsd:string)
dc:title Sparse Matrix Operations on Multi-core Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document