Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/parco/Perez-RamasAPMMH05
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Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
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Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
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