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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/parelec/PierzchlewskiSNRW06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrzej_Rybarczyk>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Blazej_Nowakowski>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacek_Pierzchlewski>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pawel_Sniatala>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wojciech_Wencel>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FPARELEC.2006.39>
foaf:homepage <https://doi.org/10.1109/PARELEC.2006.39>
dc:identifier DBLP conf/parelec/PierzchlewskiSNRW06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FPARELEC.2006.39 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label FPGA Chip as a System Master for Hardware Aided Parallel Computing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrzej_Rybarczyk>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Blazej_Nowakowski>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacek_Pierzchlewski>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pawel_Sniatala>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wojciech_Wencel>
swrc:pages 220-226 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/parelec/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/parelec/PierzchlewskiSNRW06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/parelec/PierzchlewskiSNRW06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/parelec/parelec2006.html#PierzchlewskiSNRW06>
rdfs:seeAlso <https://doi.org/10.1109/PARELEC.2006.39>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/parelec>
dc:title FPGA Chip as a System Master for Hardware Aided Parallel Computing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document