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<https://dblp.l3s.de/d2r/resource/authors/Johan_Vounckx>
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<https://dblp.l3s.de/d2r/resource/authors/Philippe_Maurine>
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<https://dblp.l3s.de/d2r/resource/authors/Johan_Vounckx>
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DBLP conf/patmos/2006
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DOI doi.org%2F10.1007%2F11847083
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ISBN 3-540-39094-4
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ISBN 3-540-39094-4
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2006
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
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Springer
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<http://dblp.uni-trier.de/db/conf/patmos/patmos2006.html>
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dc:title
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
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4148
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