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<http://dblp.uni-trier.de/rec/bibtex/conf/patmos/2007>
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<https://dblp.l3s.de/d2r/resource/authors/Lars_J._Svensson>
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<https://dblp.l3s.de/d2r/resource/authors/Nadine_Az%E2%88%9A%C2%A9mard>
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<https://dblp.l3s.de/d2r/resource/authors/Lars_J._Svensson>
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<https://dblp.l3s.de/d2r/resource/authors/Nadine_Az%E2%88%9A%C2%A9mard>
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<http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-74442-9>
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<https://doi.org/10.1007/978-3-540-74442-9>
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DBLP conf/patmos/2007
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dc:identifier
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DOI doi.org%2F10.1007%2F978-3-540-74442-9
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ISBN 978-3-540-74441-2
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ISBN 978-3-540-74441-2
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2007
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rdfs:label
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
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Springer
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<https://dblp.l3s.de/d2r/resource/conferences/patmos>
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<http://dblp.uni-trier.de/db/conf/patmos/patmos2007.html>
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dc:title
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
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4644
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