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<https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Monteiro_0001>
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<https://dblp.l3s.de/d2r/resource/authors/Lars_Svensson>
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<https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Monteiro_0001>
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<https://dblp.l3s.de/d2r/resource/authors/Lars_Svensson>
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<http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-95948-9>
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DBLP conf/patmos/2008
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DOI doi.org%2F10.1007%2F978-3-540-95948-9
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ISBN 978-3-540-95947-2
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ISBN 978-3-540-95947-2
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2009
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
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Springer
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dc:title
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
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5349
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