Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/patmos/ChenLKS07
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Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
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Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
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