UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Ioannis_Giannou>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Nikolaos_Georgoulopoulos>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FPATMOS.2018.8464148>
foaf:homepage	<https://doi.org/10.1109/PATMOS.2018.8464148>
dc:identifier	DBLP conf/patmos/Georgoulopoulos18 (xsd:string)
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dcterms:issued	2018 (xsd:gYear)
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swrc:pages	97-102 (xsd:string)
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dc:title	UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. (xsd:string)
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