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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Spyros_Blionas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Theodore_Laopoulos>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-39762-5%5F34>
foaf:homepage <https://doi.org/10.1007/978-3-540-39762-5_34>
dc:identifier DBLP conf/patmos/NikolaidisKLBB03 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-39762-5%5F34 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Instruction Level Energy Modeling for Pipelined Processors. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Theodore_Laopoulos>
swrc:pages 279-288 (xsd:string)
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dc:title Instruction Level Energy Modeling for Pipelined Processors. (xsd:string)
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rdf:type swrc:InProceedings
rdf:type foaf:Document