Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/patmos/SierraCC18
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/patmos/SierraCC18
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Carlos_Carreras
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Gabriel_Caffarena
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Roberto_Sierra
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FPATMOS.2018.8464170
>
foaf:
homepage
<
https://doi.org/10.1109/PATMOS.2018.8464170
>
dc:
identifier
DBLP conf/patmos/SierraCC18
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FPATMOS.2018.8464170
(xsd:string)
dcterms:
issued
2018
(xsd:gYear)
rdfs:
label
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Carlos_Carreras
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Gabriel_Caffarena
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Roberto_Sierra
>
swrc:
pages
7-12
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/patmos/2018
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/patmos/SierraCC18/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/patmos/SierraCC18
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/patmos/patmos2018.html#SierraCC18
>
rdfs:
seeAlso
<
https://doi.org/10.1109/PATMOS.2018.8464170
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/patmos
>
dc:
title
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document