[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/patmos/TangZBM10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Amir_Zjajo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michel_Berkelaar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nick_van_der_Meijs>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qin_Tang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-17752-1%5F19>
foaf:homepage <https://doi.org/10.1007/978-3-642-17752-1_19>
dc:identifier DBLP conf/patmos/TangZBM10 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-17752-1%5F19 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amir_Zjajo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michel_Berkelaar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nick_van_der_Meijs>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qin_Tang>
swrc:pages 190-199 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/patmos/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/patmos/TangZBM10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/patmos/TangZBM10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/patmos/patmos2010.html#TangZBM10>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-17752-1_19>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/patmos>
dc:title Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document