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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/patmos/TeichmannFHAS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Doris_Schmitt-Landsiedel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ettore_Amirante>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%C4%BErgen_Fischer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_Teichmann>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephan_Henzler>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11556930%5F65>
foaf:homepage <https://doi.org/10.1007/11556930_65>
dc:identifier DBLP conf/patmos/TeichmannFHAS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11556930%5F65 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Power-Clock Gating in Adiabatic Logic Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Doris_Schmitt-Landsiedel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ettore_Amirante>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%C4%BErgen_Fischer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_Teichmann>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephan_Henzler>
swrc:pages 638-646 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/patmos/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/patmos/TeichmannFHAS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/patmos/TeichmannFHAS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/patmos/patmos2005.html#TeichmannFHAS05>
rdfs:seeAlso <https://doi.org/10.1007/11556930_65>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/patmos>
dc:title Power-Clock Gating in Adiabatic Logic Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document