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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/pdp/HoggHL96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_W._Lloyd>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R._S._Hogg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/W._I._Hughes>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FEMPDP.1996.500598>
foaf:homepage <https://doi.org/10.1109/EMPDP.1996.500598>
dc:identifier DBLP conf/pdp/HoggHL96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FEMPDP.1996.500598 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label A Novel Asynchronous ALU for Massively Parallel Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_W._Lloyd>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R._S._Hogg>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/W._I._Hughes>
swrc:pages 282-289 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/pdp/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/pdp/HoggHL96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/pdp/HoggHL96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/pdp/pdp1996.html#HoggHL96>
rdfs:seeAlso <https://doi.org/10.1109/EMPDP.1996.500598>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/pdp>
dc:subject parallel architectures; systolic arrays; asynchronous circuits; novel asynchronous ALU; massively parallel architectures; self timed asynchronous bit serial massively parallel architecture; clocked control; fixed word length; small magnitude data; clock skew; self timed communication techniques; arithmetic logic unit; self timed single instruction systolic array; ST-SISA; self timed delay insensitive techniques (xsd:string)
dc:title A Novel Asynchronous ALU for Massively Parallel Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document