Area and Power-efficient Innovative Network-on-Chip Architecurte.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/pdp/WangHLB10
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2010
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Area and Power-efficient Innovative Network-on-Chip Architecurte.
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Network-on-Chip (NoC); interconnection network; power-efficient; power-optimization; area-efficient; system-on-chip (SoC)
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Area and Power-efficient Innovative Network-on-Chip Architecurte.
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